1. Field of the Invention
The present invention relates generally to dynamic type semiconductor memory devices having separate read and write buses, and more particularly, to an improved construction thereof and operating method therefor, wherein access time for reading of data from the device is reduced to provide high-speed operation.
2. Description of the Prior Art
Recently, it has been desired in a highly integrated memory device such as a dynamic MOSRAM (i.e., a dynamic random access memory using MOS transistors) to attain a large-scale integration for increasing a storage capacity thereof and to increase a speed of reading operation by considerably reducing access time (i.e., time required for reading of data).
FIG. 1 is a schematic diagram showing an entire construction of a conventional semiconductor memory device. First, the construction will be described in the following.
Referring to FIG. 1, the conventional semiconductor memory device comprises a memory cell array 101 having a plurality of memory cells arranged in rows and in columns to have a folded bit line structure. An address buffer 102 for generating an internal row address and an internal column address upon receipt of an address signal ADD applied externally, a row decoder 103 for selecting memory cells of one row out of the memory cell array 101 upon receipt of the internal row address from the address buffer 102 and a column decoder 104 for selecting memory cells of one column (a bit line pair) out of the memory cell array 101 in response to the internal column address signal from the address buffer 102 are provided for memory cell selection. A block 105 (including a sense amplifier portion and an I/O portion) is provided for amplifying a signal potential difference on the bit line pair and connecting the selected bit line pair to the I/O portion in response to a column decoded signal from the column decoder 104. A write-in buffer 106 for receiving externally applied data D.sub.IN to be written and converting the same to a pair of complementary data (D.sub.IN and D.sub.IN for example) to transfer the pair of the data to the I/O portion of the block 105 and a read-out buffer 107 for receiving the data from the I/O portion of the block 105 and outputting the same as an output signal D.sub.OUT to outside are provided for writing data into and reading data from a selected memory cell(s). Further, a clock generator 108 for generating signals such as a row address strobe signal RAS and a column address strobe signal CAS is provided for applying timing to start a memory cycle, to receive an address signal and to effect other operation.
The row address strobe signal RAS from the clock generator 108 is applied to the address buffer 102, the row decoder 108 and the like, while the column address strobe signal CAS is applied to the address buffer the column decoder 104 and, the like.
As shown in FIGS. 2a-c, the row address strobe signal RAS applies timing for accepting a row address in the address buffer 102 and the column address strobe signal CAS applies timing for accepting a column address in the address buffer 102. In this configuration, row addresses and column addresses are supplied to the address buffer 102 sequentially. Timing for decoding the address signal in the row decoder 103 and that in the column decoder 104 are determined by the signal RAS and CAS, respectively.
FIG. 3 is a diagram showing a configuration of a main part of the memory cell array portion shown in FIG. 1, an example of a construction of the block 150 indicated by dotted lines being represented in a concrete manner.
FIG. 3 typically shows a pair of bit lines BL and BL of the folded bit line structure. In FIG. 3, the pair of bit lines BL and BL forms a pair of folded bit lines. In other words, complementary signals appear on the bit lines BL and BL. A plurality of word lines are provided in a direction perpendicular to the bit lines BL and BL. In FIG. 3, only a single word line WL is shown typically. Memory cells are provided at intersections of the word lines and the bit lines. The memory cells are arranged in rows and in columns. In FIG. 3, only one memory cell 1 provided at an intersection of the bit line BL and the word line WL is typically shown. The memory cell 1 is of a 1-transistor and 1-capacitor type. It comprises a memory cell capacitor C0 for storing information, and an N channel MOS (metal-oxide-semiconductor) transistor Q0 which is turned on in response to a signal supplied on the word line WL to connect the memory cell capacitor C0 to the bit line BL. A cell plate (an electrode) of the memory cell capacitor is connected at a predetermined potential V.sub.SG.
Flip-flop sense amplifiers 2 and 3 are provided to differentially amplify the signal potential difference on the pair of bit lines BL and BL. The sense amplifier 2 comprises N channel MOS transistors Q1 and Q2, which discharge a potential on the lower potential bit line to a ground potential. A gate of the MOS transistor Q1 is connected to the bit line BL and a drain thereof is connected to the bit line BL. A gate of the MOS transistor Q2 is connected to the bit line BL and a drain thereof is connected to the bit line BL. Sources of the MOS transistors Q1 and Q2 are connected to a node N1. The node N1 is connected with a sense amplifier activation means 4 for activating the sense amplifier 2 in response to a sense amplifier activation signal S0. The sense amplifier activation means 4 comprises an N channel MOS transistor Q5 which is turned on in response to the sense amplifier activation signal S0 to connect the node N1 to the ground potential.
The sense amplifier 3 comprises P channel MOS transistors Q3 and Q4, which are activated in response to a signal from a sense amplifier activation means 5 to charge a potential on the higher potential bit line to a power supply potential Vcc. A gate of the MOS transistor Q3 is connected to the bit line BL and a gate of the MOS transistor Q4 is connected to the bit line BL. Conduction terminals of the MOS transistors Q3 and Q4 are connected to the bit lines BL and BL, respectively, the other conduction terminals thereof being connected in common to a node N2. An output of the sense amplifier activation means 5 is transferred to the node N2. The sense amplifier activation means 5 is turned on in response to a sense amplifier activation signal S0. It comprises a P channel MOS transistor Q6 for applying the power supply potential Vcc to the node N2.
There is provided precharge/equalizing means 6 for precharging the pair of bit lines BL and BL and equalizing the potentials thereof in response to an equalizing signal EQ. The precharge/equalizing means 6 precharges the respective bit lines to a predetermined potential and equalizing the potentials of the bit lines before start of and after completion of a memory cycle (i.e., in standby time). The precharge/equalizing means 6 comprises: an equalization N channel MOS transistor Q7 which is turned on in response to the equalizing signal EQ to electrically short-circuit the pair of the bit lines BL and BL; a precharge N channel MOS transistor Q8 which applies a precharge potential V.sub.BL to the bit line BL in response to the equalizing signal EQ; and a precharge N channel MOS transistor Q9 which is turned on in response to the equalizing signal EQ to apply the precharge potential V.sub.BL to the bit line BL. The precharge potential V.sub.BL is normally generated by an internal voltage generating circuit and it is set to a predetermined potential (for example, a half of the power supply voltage Vcc, i.e., Vcc/2).
The bit lines BL and BL are further connected with N channel MOS transistors Q10 and Q11, respectively, which are turned on in response to a bit line pair selection signal (i.e., a column decode signal) Y from the column decoder (not shown in FIG. 3) to connect the bit lines BL and BL to data input/output buses I/O and I/O. The pair of data input/output buses I/O and I/O are precharged at a predetermined potential V.sub.BL ' by N channel MOS transistors Q22 and Q23 which are turned on in response to a clock signal CLK. The pair of data input/output buses I/O and I/O communicate data through input/output buffers.
FIGS. 4a-d are signal waveforms diagram showing reading operation of the conventional semiconductor memory device, the same reference characters as in FIG. 3 representing potential changes in the corresponding portions. Referring to FIGS. 3 and 4, operation of the conventional semiconductor memory device will be described in the following.
Before time T1, the equalizing signal EQ is at a high level and the equalizing transistor Q7 and the precharge transistors Q8 and Q9 are all in the on state, with the bit lines BL and BL being precharged at the predetermined potential V.sub.BL.
When the equalizing signal EQ changes from the high level to a low level at the time T1, the transistors Q7, Q8 and Q9 are all turned off and the precharge/equalizing operation of the bit lines BL and BL is terminated to cause the bit lines BL and BL to be in an electrically floating state, whereby the device is ready for a start of the next memory cycle.
When a word line WL is selected in response to a row decode signal from the row decoder at time T2, the potential of the word line WL changes from the low level to the high level. As a result, the transistor Q0 of the memory cell 1 to be connected to the word line WL is turned on and the memory capacitor C0 is connected to the bit line BL. Accordingly, a potential change dependent on information of the memory cell 1 occurs in the bit line BL. If information "1" is stored in the memory cell 1, the potential of the bit line BL becomes slightly higher than the precharge potential as shown by solid lines in FIGS. 4a-d with the potential of the bit line BL being maintained at the precharge potential.
If the potential of the read-out signal on the pair of bit lines BL and BL becomes stable, the sense amplifier activation signals S0 and S0 begin to be raised and lowered, respectively, at time T3. Thus, the MOS transistors Q5 and Q6 are turned on, and the node N1 is discharged to the ground potential, while the node N2 is charged to the power supply potential Vcc. As a result, the flip-flop sense amplifiers 2 and 3 are both activated, and the bit line BL of the higher potential out of the pair of bit lines BL and BL is charged to the power supply potential Vcc through the sense amplifier 3, while the bit line BL of the lower potential is discharged to the ground potential through the sense amplifier 2. Thus, the slight signal potential difference on the pair of bit lines BL and BL is amplified by the activation of the sense amplifiers 2 and 3.
When the bit line pair selection signal (i.e., the column decode signal) Y from the column decoder 104 rises to the high level at time T4 after the amplification by the sense amplifiers, the MOS transistors Q10 and Q11 are turned on and the potentials on the bit lines BL and BL are applied to the data input/output buses I/O and I/O. The potentials applied to the data input/output buses I/O and I/O are amplified by amplifying means such as preamplifiers, not shown, or the like and then transmitted to an external portion through the data output buffers and external output terminals (not shown), the pair of data buses I/O and I/O being in the floating state at the time of transmission of the data.
When the transmission of the data to the external output terminals is completed, the potential of the word line WL changes from the high level to the low level at time T5 and the level of the bit line pair selection signal Y also changes from the high level to the low level. As a result, the potential on the pair of data input/output buses I/O to the precharge potential V.sub.BL '.
Then, at time T6, sense amplifier activation signals S0 and S0 change from the high level to the low level and from the low level to the high level, respectively, so that the sense amplifiers 2 and 3 are both in a non-active state. At the same time, the equalizing signal EQ rises to the high level to activate the precharge/equalizing means 6 and, thus, the bit lines BL and BL are precharged to the predetermined potential V.sub.BL and the potentials on the pair of the bit lines BL and BL are equalized.
Thus, the outline of the data reading operation was described. On the other hand, in data writing operation, timing of a signal waveform is the same as shown in FIG. 4 and the data flows in a direction opposite to that in the case of the reading operation, i.e., in the direction from the data input buffers to a selected memory cell through the pair of data input/output buses. More specifically, the data input buffers to a selected memory cell through the pair of data input/output buses. More specifically, the data to be written, supplied from an external portion through the data write-in buffer (not shown) are transferred to the data input/output buses I/O and I/O in a complementary form (such as D.sub.IN and D.sub.IN). After sequential operations from the time T1 to the time T3, the bit line selection signal Y changes from the low level to the high level at the time T4. Then, the MOS transistors Q10 and Q11 are turned on and the signal potentials on the data input/output buses I/O and I/O are applied to a selected memory cell, whereby the data is written, In this case, the sense amplifiers 2 and 3 are activated at the time T3 and the signal potential difference on the bit lines BL and BL is amplified after the change of the word line WL to the high level. However, even if the signal level amplified by the sense amplifiers 2 and/or 3 is opposite to the signal potential level of the write-in data, the signal potential according to the write-in data appears on the bit lines BL and BL since the write-in data is transferred onto the data input/output buses I/O and I/O through the external data input buffer. More specifically, the drivability of the data input buffer (or write-in buffer) is designed to be larger than the latching ability of the sense amplifiers, and therefore write-in data can reverse the data latched by a sense amplifier. Thus, the write-in data is written into the selected memory cell through the MOS transmitter Q0 in the on state.
As described above, in the construction of the conventional, semiconductor memory device, data is read out and written from and into the corresponding memory cell through the same data input/output bus pair I/O and I/O. Accordingly, even in reading data, the pair of the bit lines BL and BL are connected with the pair of the data input/output buses I/O and I/O through the MOS transistors Q10 and Q11, respectively. In order to read data at high speed, it is preferable to connect the pair of the bit lines with the pair of the data input/output buses as fast as possible. However, if the connection between the pair of the bit lines and the pair of the data input/output buses is made in a period from the time T2 for raising the potential of the word line WL to the time T3 for starting sensing operation by activating of the sense amplifiers 2 and 3 for example as shown in FIG. 4, load capacitance of the data input/output buses is applied to the bit lines to cause the read-out signal level on the bit lines to be lowered. As a result, the sense amplifiers could not perform stable sensing operation and erroneous operation might occur. Accordingly, it is necessary to connect the bit line pair with the data input/output bus pair after the sense amplifiers 2 and 3 are activated and the signal potentials on the bit lines BL and BL become stable. The connection between the selected pair of the bit lines and the pair of the data input/output buses can not be made before the time T3 on reading out data. Consequently, the conventional device involves disadvantages that increase of speed in reading operation is limited and that it is difficult to reduce access time. More specifically, if the conventional device has the construction using the same pair of the data input/output buses for reading and wiring of data, it is difficult to reduce access time in the data reading operation.
S. Watanabe et al. propose, in "BiCMOS CIRCUIT TECHNOLOGY FOR HIGH SPEED DRAMs", '87 VLSI SYMPOSIUM, Digest of Technical Papers, 1897, pp. 79-80, a DRAM with a write data bus and a read data bus separately provided for the purpose of high-speed reading. In Watanabe's DRAM, a BiCMOS differential sense amplifier separate from a conventional flip-flop type sense amplifier is additionally provided between the read-data bus and respective bit line pairs.
FIG. 5 shows the circuit diagram of DRAM disclosed by Watanabe et al. in the above prior art reference.
Referring to FIG. 5, the write-data bus IL, IL and the read-data bus OL, OL are separately provided on each side of the bit lines. The bit lines BL, BL are isolated from the write data bus IL, IL in a reading mode in response to a signal WRITE. Between the read-data bus and a bit line pair a BiCMOS differential sense amplifier is provided. The input stage of the BiCMOS sense amplifier is connected through clocked inverters with paired bit lines. Between the read-data bus and a data output (D.sub.OUT) buffer a level shift circuit for shifting a signal voltage level on the read-data bus OL, OL and another BiCMOS sense amplifier for differentially amplifying the output of the level shift circuit to apply the same to the D.sub.OUT buffer.
The write-data bus comprises a pair of signal lines IL and IL connected to a bit line BL and a complementary bit line BL, respectively. Similarly, the read-data bus comprises a pair of signal line OL and OL for receiving data frame the bit line BL and the complementary bit line BL, respectively, through the BiCMOS differential amplifier. In FIG. 5, the signals CSL1 and CSL2 denotes column decoded signals from a column decoder (not shown). Operation of the DRAM is described where a memory cell storing data of "0" is selected to be connected to the bit line BL1, referring to FIG. 6 showing a waveform of the main nodes at a reading operation.
In reading, the signal WRITE is at a low level to isolate all of the bit lines from the write-data bus. First, a word line WL is selected in response to an externally applied row address to be activated. Then, data stored in the memory cells connected to the selected word line WL are transferred to the corresponding bit liens BL1, BL2 . . . , resulting in a small change of voltage on the bit lines depending on transferred data. This small change of the bit line voltage causes a conductance modulating of the clocked CMSO inverter. This conductance modulation is applied tot he input stage of the BiCMOS sense amplifier in response to the column decoded signal CSL1. Then, the BiCMOS sense amplifier is already activated by the signal CSL1 to amplify the received small signal in a short period of time owing to its high current drivability. Data on the bit line BL1 is transferred to the read-data line OL. The signal voltage on the read-data line OL is shifted in the level and amplified by the next circuit of the level shift circuit and the another BiCMSO differential amplifier.
The amplified data RD, RD is applied to the D.sub.OUT buffer. Then the data D.sub.OUT is outputted from the D.sub.OUT buffer. At the same time, the conventional flip-flop type sense amplifier is activated to restore memory cell data. Thus, the data of the selected memory cell is read out before or at the same time of activation of the conventional flip-flop type sense amplifiers, providing high speed reading.
In writing the signal WRITE is at a high level, and writing data is performed through the write-data bus IL, IL in the same manner as that in the conventional DRAM shown in FIG. 3.
In this prior art, however, every bit line is not directly connected to the input stage of the BiCMOS sense amplifier, but indirectly connected thereto through the clocked inverter.
A clocked inverter typically comprises the circuit configuration as shown in FIG. 7. The clocked inverter consists of a CMOS inverter formed of complimentarily connected P channel MOS load transistor QP1 and N channel MOS driver transistor QND and cut-off switch transistors QPC and QNC which are connected to the power supply Vc and the ground, respectively. The cut-off switch transistors QPC and QNC inhibit the operation of the inverter (that is, inversion of a received input IN to an output OUT) when the control clock CLOCK is at a low level and the complement thereof CLOCK is at a high level. On the other hand, the clocked inverter acts as a normal inverter when the control clock CLOCK goes high.
One reason why the prior art uses the clocked inverter in addition to the BiCMOS differential sense amplifier is that input impedance of a bipolar transistor is in general considerably lower than that of an MOS transistor.
Thus, an isolating device is required to avoid adverse interference to a bit line voltage and therefore to the amplifying operation of a conventional CMOS flip-flop type sense amplifier.
Another reason is to supply the base current to the bipolar transistors in the BiCMOS differential sense amplifier and pre-amplify the input swing of the simple differential sense amplifier.
Consequently, the prior art has a disadvantage in delaying the read operation because a clocked inverter is inevitably required and hence the read operation thereof is inherently delayed by the inverter
Further, the clocked inverter comprises at least four transistors, leading to another disadvantage in view of area consumption in achieving a larger scale integration.
Furthermore, the simple differential sense amplifier of the prior art is not sufficient for the high speed operation because it does not have a positive feed-back to accelerate the amplification of the input voltage to supply the output voltage.